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2.0 amp output current igbt gate drive optocoupler technical data hcpl-3120 HCPL-J312 hcnw3120 features ?2.0 a minimum peak output current ?15 kv/ s minimum common mode rejection (cmr) at v cm = 1500 v ?0.5 v maximum low level output voltage (v ol ) eliminates need for negative gate drive ?i cc = 5 ma maximum supply current ?under voltage lock-out protection (uvlo) with hysteresis ?wide operating v cc range: 15 to 30 volts ?500 ns maximum switching speeds ?industrial temperature range: -40 c to 100 c ?safety approval ul recognized 3750 vrms for 1 min. for hcpl-3120/j312 5000 vrms for 1 min. for hcnw3120 csa approval iec/en/din en 60747-5-2 approved v iorm = 630 vpeak for hcpl-3120 (option 060) v iorm = 891 vpeak for HCPL-J312 v iorm = 1414 vpeak for hcnw3120 applications ?igbt/mosfet gate drive ?ac/brushless dc motor drives ?industrial inverters ?switch mode power supplies a 0.1 f bypass capacitor must be connected between pins 5 and 8. caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. functional diagram truth table v cc - v ee v cc - v ee ?ositive going ?egative going led (i.e., turn-on) (i.e., turn-off) v o off 0 - 30 v 0 - 30 v low on 0 - 11 v 0 - 9.5 v low on 11 - 13.5 v 9.5 - 12 v transition on 13.5 - 30 v 12 - 30 v high 1 3 shield 2 4 8 6 7 5 n/c cathode anode n/c v cc v o v o v ee 1 3 shield 2 4 8 6 7 5 n/c cathode anode n/c v cc n/c v o v ee hcnw3120 hcpl-3120/j312
2 description the hcpl-3120 contains a gaasp led while the HCPL-J312 and the hcnw3120 contain an algaas led. the led is optically coupled to an integrated circuit with a power output stage. these optocouplers are ideally suited for driving power igbts and mosfets used in motor control inverter applications. the high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. the voltage and current supplied by these optocouplers make them ideally suited for directly driving igbts with ratings up to 1200 v/100 a. for igbts with higher ratings, the hcpl-3120 series can be used to drive a discrete power stage which drives the igbt gate. the hcnw3120 has the highest insulation voltage of v iorm = 1414 vpeak in the iec/ en/din en 60747-5-2. the HCPL-J312 has an insulation voltage of v iorm = 891 vpeak and the v iorm = 630 vpeak is also available with the hcpl- 3120 (option 060). selection guide part number hcpl-3120 HCPL-J312 hcnw3120 hcpl-3150* output peak current ( i o ) 2.0 a 2.0 a 2.0 a 0.5 a iec/en/din en v iorm = 630 vpeak v iorm = 891 vpeak v iorm = 1414 vpeak v iorm = 630 vpeak 60747-5-2 approval (option 060) (option 060) *the hcpl-3150 data sheet available. contact agilent sales representative or authorized distributor. ordering information specify part number followed by option number (if desired) example: hcpl-3120#xxxx 060 = iec/en/din en 60747-5-2, v iorm = 630 vpeak (hcpl-3120 only) 300 = gull wing surface mount option 500 = tape and reel packaging option xxxe = lead free option option 500 contains 1000 units (hcpl-3120/j312), 750 units (hcnw3120) per reel. other options contain 50 units (hcpl-3120/j312), 42 units (hcnw312) per tube. option data sheets available. contact agilent sales representative or authorized distributor. remarks: the notation ??is used for existing products, while (new) products launched since 15th july 2001 and lead free option will use ?
3 package outline drawings hcpl-3120 outline drawing (standard dip package) hcpl-3120 gull wing surface mount option 300 outline drawing 1.080 0.320 (0.043 0.013) 2.54 0.25 (0.100 0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. 5 typ. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010) 9.65 0.25 (0.380 0.010) 1.78 (0.070) max. 1.19 (0.047) max. a xxxxz yyww date code dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 option code* type number * marking code letter for option numbers. "v" = option 060 option numbers 300 and 500 not marked. note: floating lead protrusion is 0.25 mm (10 mils) max. 3.56 0.13 (0.140 0.005) 0.635 0.25 (0.025 0.010) 12 nom. 9.65 0.25 (0.380 0.010) 0.635 0.130 (0.025 0.005) 7.62 0.25 (0.300 0.010) 5 6 7 8 4 3 2 1 9.65 0.25 (0.380 0.010) 6.350 0.25 (0.250 0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 0.320 (0.043 0.013) 3.56 0.13 (0.140 0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002)
4 package outline drawings HCPL-J312 outline drawing (standard dip package) HCPL-J312 gull wing surface mount option 300 outline drawing 1.080 0.320 (0.043 0.013) 2.54 0.25 (0.100 0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. 5 typ. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010) 9.65 0.25 (0.380 0.010) 1.78 (0.070) max. 1.19 (0.047) max. a xxxxz yyww date code dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 option code* type number * marking code letter for option numbers. "v" = option 060 option numbers 300 and 500 not marked. note: floating lead protrusion is 0.5 mm (20 mils) max. 3.56 0.13 (0.140 0.005) 0.635 0.25 (0.025 0.010) 12 nom. 9.65 0.25 (0.380 0.010) 0.635 0.130 (0.025 0.005) 7.62 0.25 (0.300 0.010) 5 6 7 8 4 3 2 1 9.80 0.25 (0.386 0.010) 6.350 0.25 (0.250 0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 0.320 (0.043 0.013) 3.56 0.13 (0.140 0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). note: floating lead protrusion is 0.5 mm (20 mils) max. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002)
5 hcnw3120 outline drawing (8-pin wide body package) hcnw3120 gull wing surface mount option 300 outline drawing 5 6 7 8 4 3 2 1 11.15 0.15 (0.442 0.006) 1.78 0.15 (0.070 0.006) 5.10 (0.201) max. 1.55 (0.061) max. 2.54 (0.100) typ. dimensions in millimeters (inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 7 typ. 0.254 + 0.076 - 0.0051 (0.010 + 0.003) - 0.002) 11.00 (0.433) 9.00 0.15 (0.354 0.006) max. 10.16 (0.400) typ. a hcnwxxxx yyww date code type number 0.51 (0.021) min. 0.40 (0.016) 0.56 (0.022) 3.10 (0.122) 3.90 (0.154) 1.00 0.15 (0.039 0.006) 7 nom. 12.30 0.30 (0.484 0.012) 0.75 0.25 (0.030 0.010) 11.00 (0.433) 5 6 7 8 4 3 2 1 11.15 0.15 (0.442 0.006) 9.00 0.15 (0.354 0.006) 1.3 (0.051) 13.56 (0.534) 2.29 (0.09) land pattern recommendation 1.78 0.15 (0.070 0.006) 4.00 (0.158) max. 1.55 (0.061) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 0.254 + 0.076 - 0.0051 (0.010 + 0.003) - 0.002) max.
6 recommended pb-free ir profile solder reflow temperature profile 0 time (seconds) temperature ( c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160 c 140 c 150 c peak temp. 245 c peak temp. 240 c peak temp. 230 c soldering time 200 c preheating time 150 c, 90 + 30 sec. 2.5 c 0.5 c/sec. 3 c + 1 c/ 0.5 c tight typical loose room temperature preheating rate 3 c + 1 c/ 0.5 c/sec. reflow heating rate 2.5 c 0.5 c/sec. 217 c ramp-down 6 c/sec. max. ramp-up 3 c/sec. max. 150 - 200 c 260 +0/-5 c t 25 c to peak 60 to 150 sec. 20-40 sec. time within 5 c of actual peak temperature t p t s preheat 60 to 180 sec. t l t l t smax t smin 25 t p time temperature notes: the time from 25 c to peak temperature = 8 minutes max. t smax = 200 c, t smin = 150 c
7 regulatory information agency/standard hcpl-3120 HCPL-J312 hcnw3120 underwriters laboratory (ul) ??? recognized under ul 1577, component recognition program, category, file e55361 canadian standards association (csa) ??? file ca88324, per component acceptance notice #5 iec/en/din en 60747-5-2 ??? option 060 insulation and safety related specifications value hcpl- hcpl- hcnw parameter symbol 3120 j312 3120 units conditions minimum external l(101) 7.1 7.4 9.6 mm measured from input terminals to air gap (clearance) output terminals, shortest distance through air. minimum external l(102) 7.4 8.0 10.0 mm measured from input terminals to tracking (creepage) output terminals, shortest distance path along body. minimum internal 0.08 0.5 1.0 mm insulation thickness between emitter plastic gap and detector; also known as distance (internal clearance) through insulation. tracking resistance cti >175 >175 >200 volts din iec 112/vde 0303 part 1 (comparative tracking index) isolation group iiia iiia iiia material group (din vde 0110, 1/89, table 1)
8 iec/en/din en 60747-5-2 insulation related characteristics hcpl-3120 description symbol option 060 HCPL-J312 hcnw3120 unit installation classification per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms i-iv i-iv i-iv for rated mains voltage 300 v rms i-iv i-iv i-iv for rated mains voltage 450 v rms i-iii i-iii i-iv for rated mains voltage 600 v rms i-iii i-iv for rated mains voltage 1000 v rms i-iii climatic classification 55/100/21 55/100/21 55/100/21 pollution degree (din vde 0110/1.89) 2 2 2 maximum working insulation voltage v iorm 630 891 1414 v peak input to output test voltage, method b* v pr 1181 1670 2652 v peak v iorm x 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5pc input to output test voltage, method a* v pr 945 1336 2121 v peak v iorm x 1.5 = v pr , type and sample test, t m = 60 sec, partial discharge < 5pc highest allowable overvoltage* v iotm 6000 6000 8000 v peak (transient overvoltage, t ini = 10 sec) safety limiting values ?maximum values allowed in the event of a failure, also see figure 37. case temperature t s 175 175 150 c input current i s input 230 400 400 ma output power p s output 600 600 700 mw insulation resistance at t s , v io = 500 v r s 10 9 10 9 10 9 ? *refer to the iec/en/din en 60747-5-2 section (page 1-6/8) of the isolation control component designer's catalog for a detailed description of method a/b partial discharge test profiles. note: these optocouplers are suitable for ?afe electrical isolation?only within the safety limit data. maintenance of the safety d ata shall be ensured by means of protective circuits. surface mount classification is class a in accordance with cecc 00802. all agilent data sheets report the creepage and clearance inherent to the optocoupler component itself. these dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. however, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. for creep- age, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. there are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.
9 recommended operating conditions parameter symbol min. max. units power supply voltage (v cc - v ee ) 15 30 volts input current (on) hcpl-3120 i f(on) 7 16 ma HCPL-J312 hcnw3120 10 input voltage (off) v f(off) -3.0 0.8 v operating temperature t a -40 100 c absolute maximum ratings parameter symbol min. max. units note storage temperature t s -55 125 c operating temperature t a -40 100 c average input current i f(avg) 25 ma 1 peak transient input current i f(tran) 1.0 a (<1 s pulse width, 300 pps) reverse input voltage hcpl-3120 v r 5 volts HCPL-J312 3 hcnw3120 ?igh?peak output current i oh(peak) 2.5 a 2 ?ow?peak output current i ol(peak) 2.5 a 2 supply voltage (v cc - v ee ) 0 35 volts input current (rise/fall time) t r(in) / t f(in) 500 ns output voltage v o(peak) 0v cc volts output power dissipation p o 250 mw 3 total power dissipation p t 295 mw 4 lead solder hcpl-3120 260 c for 10 sec., 1.6 mm below seating plane temperature HCPL-J312 hcnw3120 260 c for 10 sec., up to seating plane solder reflow temperature profile see package outline drawings section
10 electrical specifications (dc) over recommended operating conditions (t a = -40 to 100 c, i f(on) = 7 to 16 ma, v f(off) = -3.0 to 0.8 v, v cc = 15 to 30 v, v ee = ground) unless otherwise specified. parameter symbol device min. typ.* max. units test conditions fig. note high level i oh 0.5 1.5 a v o = (v cc - 4 v) 2, 3, 5 2.0 a v o = (v cc - 15 v) 17 2 low level i ol 0.5 2.0 a v o = (v ee + 2.5 v) 5, 6, 5 2.0 a v o = (v ee + 15 v) 18 2 high level v oh (v cc - 4) (v cc - 3) v i o = -100 ma 1, 3, 6, 7 output voltage 19 low level v ol 0.1 0.5 v i o = 100 ma 4, 6, output voltage 20 high level i cch 2.5 5.0 ma output open, 7, 8 supply current i f = 7 to 16 ma low level i ccl 2.5 5.0 ma output open, supply current v f = -3.0 to +0.8 v threshold input i flh hcpl-3120 2.3 5.0 ma i o = 0 ma, 9, 15, current low HCPL-J312 1.0 v o > 5 v 21 to high hcnw3120 2.3 8.0 threshold input v fhl 0.8 v voltage high to low input forward v f hcpl-3120 1.2 1.5 1.8 v i f = 10 ma 16 voltage HCPL-J312 1.6 1.95 hcnw3120 temperature ? v f / ? t a hcpl-3120 -1.6 mv/ ci f = 10 ma coefficient HCPL-J312 -1.3 of forward hcnw3120 voltage input reverse bv r hcpl-3120 5 v i r = 10 a breakdown HCPL-J312 3 i r = 100 a voltage hcnw3120 input c in hcpl-3120 60 pf f = 1 mhz, capacitance HCPL-J312 70 v f = 0 v hcnw3120 uvlo threshold v uvlo+ 11.0 12.3 13.5 v v o > 5 v, 22, i f = 10 ma 34 v uvlo 9.5 10.7 12.0 uvlo hysteresis uvlo hys 1.6 *all typical values at t a = 25 c and v cc - v ee = 30 v, unless otherwise noted. output current output current
11 switching specifications (ac) over recommended operating conditions (t a = -40 to 100 c, i f(on) = 7 to 16 ma, v f(off) = -3.0 to 0.8 v, v cc = 15 to 30 v, v ee = ground) unless otherwise specified. parameter symbol min. typ.* max. units test conditions fig. note propagation delay t plh 0.10 0.30 0.50 s rg = 10 ? , 10, 11, 16 time to high cg = 10 nf, 12, 13, output level f = 10 khz, 14, 23 propagation delay t phl 0.10 0.30 0.50 s time to low output level pulse width pwd 0.3 s17 distortion propagation delay pdd -0.35 0.35 s 35, 36 12 difference between (t phl - t plh ) any two parts rise time t r 0.1 s23 fall time t f 0.1 s uvlo turn on t uvlo on 0.8 sv o > 5 v, i f = 10 ma 22 delay uvlo turn off t uvlo off 0.6 v o < 5 v, i f = 10 ma delay output high level |cm h | 15 30 kv/ st a = 25 c, 24 13, 14 common mode i f = 10 to 16 ma, transient v cm = 1500 v, immunity v cc = 30 v output low level |cm l | 15 30 kv/ st a = 25 c, 13, 15 common mode v cm = 1500 v, transient v f = 0 v, immunity v cc = 30 v *all typical values at t a = 25 c and v cc - v ee = 30 v, unless otherwise noted. duty cycle = 50%
12 package characteristics over recommended temperature (t a = -40 to 100 c) unless otherwise specified. parameter symbol device min. typ. max. units test conditions fig. note input-output v iso hcpl-3120 3750 v rms rh < 50%, 8, 11 momentary HCPL-J312 3750 t = 1 min., 9, 11 withstand voltage** hcnw3120 5000 t a = 25 c 10, 11 resistance r i-o hcpl-3120 10 12 ? v i-o = 500 v dc 11 (input-output) HCPL-J312 hcnw3120 10 12 10 13 t a = 25 c 10 11 t a = 100 c capacitance c i-o hcpl-3120 0.6 pf f = 1 mhz (input-output) HCPL-J312 0.8 hcnw3120 0.5 0.6 led-to-case lc 467 c/w thermocouple 28 thermal resistance led-to-detector ld 442 c/w thermal resistance detector-to-case dc 126 c/w thermal resistance *all typicals at t a = 25 c. **the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refer to your equipment level safety specification or agilent appl ication note 1074 entitled ?ptocoupler input-output endurance voltage. located at center underside of package notes: 1. derate linearly above 70 c free-air temperature at a rate of 0.3 ma/ c. 2. maximum pulse width = 10 s, maximum duty cycle = 0.2%. this value is intended to allow for component tolerances for designs with i o peak minimum = 2.0 a. see applications section for additional details on limiting i oh peak. 3. derate linearly above 70 c free-air temperature at a rate of 4.8 mw/ c. 4. derate linearly above 70 c free-air temperature at a rate of 5.4 mw/ c. the maximum led junction tempera- ture should not exceed 125 c. 5. maximum pulse width = 50 s, maximum duty cycle = 0.5%. 6. in this test v oh is measured with a dc load current. when driving capacitive loads v oh will approach v cc as i oh approaches zero amps. 7. maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. in accordance with ul1577, each optocoupler is proof tested by applying an insulation test voltage 4500 vrms for 1 second (leakage detection current limit, i i-o 5 a). 9. in accordance with ul1577, each optocoupler is proof tested by applying an insulation test voltage 4500 vrms for 1 second (leakage detection current limit, i i-o 5 a). 10. in accordance with ul1577, each optocoupler is proof tested by applying an insulation test voltage 6000 vrms for 1 second (leakage detection current limit, i i-o 5 a). 11. device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 12. the difference between t phl and t plh between any two hcpl-3120 parts under the same test condition. 13. pins 1 and 4 need to be connected to led common. 14. common mode transient immunity in the high state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in the high state (i.e., v o > 15.0 v). 15. common mode transient immunity in a low state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e., v o < 1.0 v). 16. this load condition approximates the gate load of a 1200 v/75a igbt. 17. pulse width distortion (pwd) is defined as |t phl -t plh | for any given device.
13 figure 7. i cc vs. temperature. figure 8. i cc vs. v cc . figure 4. v ol vs. temperature. figure 5. i ol vs. temperature. figure 6. v ol vs. i ol . figure 1. v oh vs. temperature. figure 2. i oh vs. temperature. figure 3. v oh vs. i oh . (v oh v cc ) high output voltage drop v -40 -4 t a temperature c 100 -1 -2 -20 0 02040 -3 60 80 i f = 7 to 16 ma i out = -100 ma v cc = 15 to 30 v v ee = 0 v i oh output high current a -40 1.0 t a temperature c 100 1.8 1.6 -20 2.0 02040 1.2 60 80 i f = 7 to 16 ma v out = (v cc - 4 v) v cc = 15 to 30 v v ee = 0 v 1.4 (v oh v cc ) output high voltage drop v 0 -6 i oh output high current a 2.5 -2 -3 0.5 -1 1.0 1.5 -5 2.0 i f = 7 to 16 ma v cc = 15 to 30 v v ee = 0 v -4 100 c 25 c -40 c v ol output low voltage v -40 0 t a temperature c -20 0.25 020 0.05 100 0.15 0.20 0.10 40 60 80 v f (off) = -3.0 to 0.8 v i out = 100 ma v cc = 15 to 30 v v ee = 0 v i ol output low current a -40 0 t a temperature c -20 4 020 1 100 2 3 40 60 80 v f (off) = -3.0 to 0.8 v v out = 2.5 v v cc = 15 to 30 v v ee = 0 v v ol output low voltage v 0 0 i ol output low current a 2.5 3 0.5 4 1.0 1.5 1 2.0 v f(off) = -3.0 to 0.8 v v cc = 15 to 30 v v ee = 0 v 2 100 c 25 c -40 c i cc supply current ma -40 1.5 t a temperature c 100 3.0 2.5 -20 3.5 02040 2.0 60 80 v cc = 30 v v ee = 0 v i f = 10 ma for i cch i f = 0 ma for i ccl i cch i ccl i cc supply current ma 15 1.5 v cc supply voltage v 30 3.0 2.5 3.5 20 2.0 25 i f = 10 ma for i cch i f = 0 ma for i ccl t a = 25 c v ee = 0 v i cch i ccl
14 figure 9. i flh vs. temperature. figure 10. propagation delay vs. v cc . figure 11. propagation delay vs. i f . figure 12. propagation delay vs. temperature. figure 14. propagation delay vs. cg. figure 13. propagation delay vs. rg. i flh low to high current threshold ma -40 0 t a temperature c 100 3 2 -20 4 02040 1 60 80 5 v cc = 15 to 30 v v ee = 0 v output = open hcpl-3120 i flh low to high current threshold ma -40 0 t a temperature c -20 5 020 1 100 2 3 40 60 80 v cc = 15 to 30 v v ee = 0 v output = open 4 HCPL-J312 i flh low to high current threshold ma -40 0 t a temperature c -20 5 020 1 100 2 3 40 60 80 v cc = 15 to 30 v v ee = 0 v output = open 4 hcnw3120 t p propagation delay ns 15 100 v cc supply voltage v 30 400 300 500 20 200 25 i f = 10 ma t a = 25 c rg = 10 ? cg = 10 nf duty cycle = 50% f = 10 khz t plh t phl t p propagation delay ns 6 100 i f forward led current ma 16 400 300 500 10 200 12 v cc = 30 v, v ee = 0 v rg = 10 ? , cg = 10 nf t a = 25 c duty cycle = 50% f = 10 khz t plh t phl 14 8 t p propagation delay ns -40 100 t a temperature c 100 400 300 -20 500 02040 200 60 80 t plh t phl i f = 10 ma v cc = 30 v, v ee = 0 v rg = 10 ? , cg = 10 nf duty cycle = 50% f = 10 khz t p propagation delay ns 0 100 rg series load resistance ? 50 400 300 10 500 30 200 40 t plh t phl v cc = 30 v, v ee = 0 v t a = 25 c i f = 10 ma cg = 10 nf duty cycle = 50% f = 10 khz 20 t p propagation delay ns 0 100 cg load capacitance nf 100 400 300 20 500 40 200 60 80 t plh t phl v cc = 30 v, v ee = 0 v t a = 25 c i f = 10 ma rg = 10 ? duty cycle = 50% f = 10 khz
15 figure 15. transfer characteristics. figure 16. input current vs. forward voltage. figure 17. i oh test circuit. v o output voltage v 0 0 i f forward led current ma 5 25 15 1 30 2 5 34 20 10 hcpl-3120 / hcnw3120 v o output voltage v 0 0 i f forward led current ma 1 35 2 5 5 15 25 34 10 20 HCPL-J312 30 i f forward current ma 1.10 0.001 v f forward voltage volts 1.60 10 1.0 0.1 1.20 1000 1.30 1.40 1.50 t a = 25 c i f v f + 0.01 100 hcpl-3120 v f forward voltage volts 1.2 1.3 1.4 1.5 i f forward current ma 1.7 1.6 1.0 i f + t a = 25 c HCPL-J312/hcnw3120 v f 0.1 0.01 0.001 10 100 1000 0.1 f v cc = 15 to 30 v 1 3 i f = 7 to 16 ma + 2 4 8 6 7 5 + 4 v i oh
16 figure 20. v ol test circuit. figure 21. i flh test circuit. figure 19. v oh test circuit. figure 18. i ol test circuit. figure 22. uvlo test circuit. 0.1 f v cc = 15 to 30 v 1 3 + 2 4 8 6 7 5 2.5 v i ol + 0.1 f v cc = 15 to 30 v 1 3 i f = 7 to 16 ma + 2 4 8 6 7 5 100 ma v oh 0.1 f v cc = 15 to 30 v 1 3 + 2 4 8 6 7 5 100 ma v ol 0.1 f v cc = 15 to 30 v 1 3 i f + 2 4 8 6 7 5 v o > 5 v 0.1 f v cc 1 3 i f = 10 ma + 2 4 8 6 7 5 v o > 5 v
17 figure 24. cmr test circuit and waveforms. figure 23. t plh , t phl , t r , and t f test circuit and waveforms. 0.1 f v cc = 15 to 30 v 10 ? 1 3 i f = 7 to 16 ma v o + + 2 4 8 6 7 5 10 khz 50% duty cycle 500 ? 10 nf i f v out t phl t plh t f t r 10% 50% 90% 0.1 f v cc = 30 v 1 3 i f v o + + 2 4 8 6 7 5 a + b v cm = 1500 v 5 v v cm ? t 0 v v o switch at b: i f = 0 ma v o switch at a: i f = 10 ma v ol v oh ? t v cm v t =
18 applications information eliminating negative igbt gate drive (discussion applies to hcpl-3120, HCPL-J312, and hcnw3120) to keep the igbt firmly off, the hcpl-3120 has a very low maximum v ol specification of 0.5 v. the hcpl-3120 realizes this very low v ol by using a dmos transistor with 1 ? (typical) on resistance in its pull down circuit. when the hcpl- 3120 is in the low state, the igbt gate is shorted to the emitter by rg + 1 ? . minimizing rg and the lead inductance from the hcpl- 3120 to the igbt gate and emitter (possibly by mounting the hcpl-3120 on a small pc board directly above the igbt) can eliminate the need for negative igbt gate drive in many applica- tions as shown in figure 25. care should be taken with such a pc board design to avoid routing the igbt collector or emitter traces close to the hcpl-3120 input as this can result in unwanted coupling of transient signals into the hcpl-3120 and degrade performance. (if the igbt drain must be routed near the hcpl- 3120 input, then the led should be reverse-biased when in the off state, to prevent the transient signals coupled from the igbt drain from turning on the hcpl-3120.) figure 25. recommended led drive and application circuit. + hvdc 3-phase ac - hvdc 0.1 f v cc = 18 v 1 3 + 2 4 8 6 7 5 270 ? hcpl-3120 +5 v control input rg q1 q2 74xxx open collector
19 selecting the gate resistor (rg) to minimize igbt switching losses. (discussion applies to hcpl-3120, hcpl- j312 and hcnw3120) step 1: calculate rg minimum from the i ol peak specifica- tion. the igbt and rg in figure 26 can be analyzed as a simple rc circuit with a voltage supplied by the hcpl-3120. (v cc ?v ee - v ol ) rg i olpeak (v cc ?v ee - 2 v) = i olpeak ( 15 v + 5 v - 2 v) = 2.5 a = 7.2 ? ? 8 ? the v ol value of 2 v in the pre- vious equation is a conservative value of v ol at the peak current of 2.5a (see figure 6). at lower rg values the voltage supplied by the hcpl-3120 is not an ideal voltage step. this results in lower peak currents (more margin) than predicted by this analysis. when negative gate drive is not used v ee in the previous equation is equal to zero volts. figure 26. hcpl-3120 typical application circuit with negative igbt gate drive. + hvdc 3-phase ac - hvdc 0.1 f v cc = 15 v 1 3 + 2 4 8 6 7 5 hcpl-3120 rg q1 q2 v ee = -5 v + 270 ? +5 v control input 74xxx open collector
20 step 2: check the hcpl-3120 power dissipation and increase rg if necessary. the hcpl-3120 total power dissipation (p t ) is equal to the sum of the emitter power (p e ) and the output power (p o ): p t = p e + p o p e = i f ? v f ? duty cycle p o = p o(bias) + p o (switching) = i cc ? (v cc - v ee ) + e sw (r g , q g ) ? f for the circuit in figure 26 with i f (worst case) = 16 ma, rg = 8 ? , max duty cycle = 80%, qg = 500 nc, f = 20 khz and t a max = 85c: p e = 16 ma ? 1.8 v ? 0.8 = 23 mw p o = 4.25 ma ? 20 v + 5.2 j ? 20 khz = 85 mw + 104 mw = 189 mw > 178 mw (p o(max) @ 85 c = 250 mw ? 15 c* 4.8 mw/c) the value of 4.25 ma for i cc in the previous equation was obtained by derating the i cc max of 5 ma (which occurs at -40 c) to i cc max at 85c (see figure 7). since p o for this case is greater than p o(max) , rg must be increased to reduce the hcpl-3120 power dissipation. p o(switching max) = p o(max) - p o(bias) = 178 mw - 85 mw = 93 mw p o(switchingmax) e sw(max) = f 93 mw = = 4.65 w 20 khz for qg = 500 nc, from figure 27, a value of e sw = 4.65 w gives a rg = 10.3 ? . p e parameter description i f led current v f led on voltage duty cycle maximum led duty cycle p o parameter description i cc supply current v cc positive supply voltage v ee negative supply voltage e sw (rg,qg) energy dissipated in the hcpl-3120 for each igbt switching cycle (see figure 27) f switching frequency figure 27. energy dissipated in the hcpl-3120 for each igbt switching cycle. esw energy per switching cycle j 0 0 rg gate resistance ? 50 6 10 14 20 4 30 40 12 qg = 100 nc qg = 500 nc qg = 1000 nc 10 8 2 v cc = 19 v v ee = -9 v
21 thermal model (discussion applies to hcpl-3120, HCPL-J312 and hcnw3120) the steady state thermal model for the hcpl-3120 is shown in figure 28. the thermal resistance values given in this model can be used to calculate the tempera- tures at each node for a given operating condition. as shown by the model, all heat generated flows through ca which raises the case temperature t c accordingly. the value of ca depends on the conditions of the board design and is, therefore, determined by the designer. the value of ca = 83 c/w was obtained from thermal measure- ments using a 2.5 x 2.5 inch pc board, with small traces (no ground plane), a single hcpl- 3120 soldered into the center of the board and still air. the absolute maximum power dissipation derating specifications assume a ca value of 83 c/w. from the thermal mode in figure 28 the led and detector ic junction temperatures can be expressed as: t je = p e ? ( lc ||( ld + dc ) + ca ) lc * dc + p d ? ( + ca ) + t a lc + dc + ld lc ? dc t jd = p e ( ?+ ca ) lc + dc + ld + p d ? ( dc || ( ld + lc ) + ca ) + t a inserting the values for lc and dc shown in figure 28 gives: t je = p e ? (256 c/w + ca ) + p d ? (57 c/w + ca ) + t a t jd = p e ? (57 c/w + ca ) + p d ? (111 c/w + ca ) + t a for example, given p e = 45 mw, p o = 250 mw, t a = 70 c and ca = 83 c/w: t je = p e ? 339 c/w + p d ? 140 c/w + t a = 45 mw ? 339 c/w + 250 m w ? 140 c/w + 70 c = 120 c t jd = p e ? 140 c/w + p d ? 194 c/w + t a = 45 mw ? 140c/w + 250 m w ? 194 c/w + 70 c = 125 c t je and t jd should be limited to 125 c based on the board layout and part placement ( ca ) specific to the application. t je = led junction temperature t jd = detector ic junction temperature t c = case temperature measured at the center of the package bottom lc = led-to-case thermal resistance ld = led-to-detector thermal resistance dc = detector-to-case thermal resistance ca = case-to-ambient thermal resistance ? ca will depend on the board design and the placement of the part. figure 28. thermal model. ld = 442 c/w t je t jd lc = 467 c/w dc = 126 c/w ca = 83 c/w* t c t a
22 led drive circuit considerations for ultra high cmr performance. (discussion applies to hcpl- 3120, HCPL-J312, and hcnw3120) without a detector shield, the dominant cause of optocoupler cmr failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector ic as shown in figure 29. the hcpl- 3120 improves cmr performance by using a detector ic with an optically transparent faraday shield, which diverts the capaci- tively coupled current away from the sensitive ic circuitry. how- ever, this shield does not eliminate the capacitive coupling between the led and optocoup- ler pins 5-8 as shown in figure 30. this capacitive coupling causes perturbations in the led current during common mode transients and becomes the major source of cmr failures for figure 29. optocoupler input to output capacitance model for unshielded optocouplers. figure 30. optocoupler input to output capacitance model for shielded optocouplers. 1 3 2 4 8 6 7 5 c ledp c ledn 1 3 2 4 8 6 7 5 c ledp c ledn shield c ledo1 c ledo2 a shielded optocoupler. the main design objective of a high cmr led drive circuit becomes keeping the led in the proper state (on or off) during common mode transients. for example, the recommended application circuit (figure 25), can achieve 15 kv/ s cmr while minimizing component complexity. techniques to keep the led in the proper state are discussed in the next two sections.
23 cmr with the led on (cmr h ). a high cmr led drive circuit must keep the led on during common mode transients. this is achieved by overdriving the led current beyond the input threshold so that it is not pulled below the threshold during a transient. a minimum led cur- rent of 10 ma provides adequate margin over the maximum i flh of 5 ma to achieve 15 kv/ s cmr. cmr with the led off (cmr l ). a high cmr led drive circuit must keep the led off (v f v f(off) ) during common mode transients. for example, during a -dv cm /dt transient in figure 31, the current flowing through c ledp also flows through the r sat and v sat of the logic gate. as long as the low state voltage developed across the logic gate is less than v f(off) , the led will remain off and no common mode failure will occur. the open collector drive circuit, shown in figure 32, cannot keep the led off during a +dvcm/dt transient, since all the current flowing through c ledn must be supplied by the led, and it is not recommended for applications requiring ultra high cmr l performance. figure 33 is an alternative drive circuit which, like the recommended application circuit (figure 25), does achieve ultra high cmr performance by shunting the led in the off state. rg 1 3 v sat 2 4 8 6 7 5 + v cm i ledp c ledp c ledn shield * the arrows indicate the direction of current flow during dv cm /dt. +5 v + v cc = 18 v 0.1 f + figure 33. recommended led drive circuit for ultra-high cmr. 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v figure 31. equivalent circuit for figure 25 during common mode transient. figure 32. not recommended open collector drive circuit. 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v q1 i ledn
24 under voltage lockout feature. (discussion applies to hcpl-3120, HCPL-J312, and hcnw3120) the hcpl-3120 contains an under voltage lockout (uvlo) feature that is designed to protect the igbt under fault conditions which cause the hcpl-3120 supply voltage (equivalent to the fully-charged igbt gate voltage) to drop below a level necessary to keep the igbt in a low resistance state. when the hcpl-3120 output is in the high state and the supply voltage drops below the hcpl-3120 v uvlo threshold (9.5 < v uvlo? < 12.0) the opto- coupler output will go into the low state with a typical delay, uvlo turn off delay, of 0.6 s. when the hcpl-3120 output is in the low state and the supply voltage rises above the hcpl- 3120 v uvlo+ threshold (11.0 < v uvlo+ < 13.5) the optocoupler output will go into the high state (assumes led is ?n? with a typical delay, uvlo turn on delay of 0.8 s. figure 34. under voltage lock out. v o output voltage v 0 0 (v cc - v ee ) supply voltage v 10 5 14 10 15 2 20 6 8 4 12 (12.3, 10.8) (10.7, 9.2) (10.7, 0.1) (12.3, 0.1)
25 figure 37. thermal derating curve, dependence of safety limiting value with case temperature per iec/en/din en 60747-5-2. t plh min maximum dead time (due to optocoupler) = (t phl max - t phl min ) + (t plh max - t plh min ) = (t phl max - t plh min ) (t phl min - t plh max ) = pdd* max pdd* min *pdd = propagation delay difference note: for dead time and pdd calculations all propagation delays are taken at the same temperature and test conditions. v out1 i led2 v out2 i led1 q1 on q2 off q1 off q2 on t phl min t phl max t plh max pdd* max (t phl- t plh ) max figure 35. minimum led skew for zero dead time. figure 36. waveforms for dead time. t phl max t plh min pdd* max = (t phl - t plh ) max = t phl max - t plh min *pdd = propagation delay difference note: for pdd calculations the propagation delays are taken at the same temperature and test conditions. v out1 i led2 v out2 i led1 q1 on q2 off q1 off q2 on ipm dead time and propagation delay specifications. (discussion applies to hcpl-3120, hcpl- j312, and hcnw3120) the hcpl-3120 includes a propagation delay difference (pdd) specification intended to help designers minimize ?ead time?in their power inverter designs. dead time is the time period during which both the high and low side power transistors (q1 and q2 in figure 25) are off. any overlap in q1 and q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. output power p s , input current i s 0 0 t s case temperature c 175 1000 50 400 125 25 75 100 150 600 800 200 100 300 500 700 900 hcnw3120 p s (mw) i s (ma) output power p s , input current i s 0 0 t s case temperature c 200 600 400 25 800 50 75 100 200 150 175 p s (mw) 125 100 300 500 700 i s (ma) for hcpl-3120 option 060 i s (ma) for HCPL-J312 hcpl-3120 option 060/HCPL-J312
to minimize dead time in a given design, the turn on of led2 should be delayed (relative to the turn off of led1) so that under worst-case conditions, transistor q1 has just turned off when transistor q2 turns on, as shown in figure 35. the amount of delay necessary to achieve this condi- tions is equal to the maximum value of the propagation delay difference specification, pdd max , which is specified to be 350 ns over the operating temperature range of -40 c to 100 c. delaying the led signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time is equivalent to the difference between the maximum and minimum propaga- tion delay difference specifica- tions as shown in figure 36. the maximum dead time for the hcpl-3120 is 700 ns (= 350 ns - (-350 ns)) over an operating temperature range of -40 c to 100 c. note that the propagation delays used to calculate pdd and dead time are taken at equal tempera- tures and test conditions since the optocouplers under consider- ation are typically mounted in close proximity to each other and are switching identical igbts. www.agilent.com/semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (916) 788-6763 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6756 2394 india, australia, new zealand: (+65) 6755 1939 japan: (+81 3) 3335-8152 (domestic/interna- tional), or 0120-61-1280 (domestic only) korea: (+65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (+65) 6755 2044 taiwan: (+65) 6755 1843 data subject to change. copyright ? 2005 agilent technologies, inc. obsoletes 5989-0308en march 1, 2005 5989-2139en

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